The present invention relates to a semiconductor integrated circuit for amplifying input signals.
FIG. 1 shows a differential amplifier that has been well known conventionally. This differential amplifier includes p-channel type MOS (xe2x80x9cpMOSxe2x80x9d) transistors TP1 and TP2, and n-channel type MOS (xe2x80x9cnMOSxe2x80x9d) transistors TN1, TN2 and TN3.
The MOS transistor TP1 receives the power source voltage VDD from the source terminal, and the drain and the gate terminals are connected to each other. The MOS transistor TP2 receives the power source voltage VDD from the source terminal, the drain terminal is connected to the node N, and the gate terminal is connected to the gate terminal of the MOS transistor TP1. The MOS transistor TN1 has its drain terminal connected to the drain terminal of the MOS transistor TP1, and the source terminal connected to the node M. The MOS transistor TN2 has its drain terminal connected to the node N, and the source terminal connected to the node M. The MOS transistor TN3 receives the ground voltage GND (=0V less than VDD) from the source terminal, and the drain terminal is connected in common to source terminals of the MOS transistors TN1 and TN2 respectively at the node M.
The MOS transistors TP1 and TP2 constitute a current mirror, and these MOS transistor function as loads on the MOS transistors TN1 and TN2 respectively. The differential amplifier receives input signals A and B from the gate terminals of the nMOS transistors TN1 and TN2 respectively, amplifies a differential voltage of these input signals, and outputs an amplified signal from the node N. The MOS transistor TN3 functions as a constant current source, and a fixed bias voltage is applied to the gate terminal of this MOS transistor TN3.
This differential amplifier is also used as an input buffer. As shown in FIG. 2, the input buffer 4 is formed on a semiconductor ship 3 and the output buffer 2 is mounted on a separate semiconductor chip 1. The output buffer 2 outputs the signal A and the signal B that is the inverse signal of the signal A via the transmission paths 5 and 6 respectively. The input buffer 4 includes the differential amplifier shown in FIG. 1. The input buffer 4 supplies output signals to a main circuit formed within the same semiconductor chip 3. The signals A and B are applied to the gate electrodes of the MOS transistors TN1 and TN2 in the input buffer 4 respectively.
When the conventional differential amplifier is applied to the input buffer 4 shown in FIG. 2, a common level of an input signal that the input buffer 4 receives is different depending on the facing output buffer 2. The common level is a center level Vc between a maximum voltage VH0 and a minimum voltage VL0 of an amplitude of the input signal (Vc=(VH0+VL0)/2). Depending on the output buffer 2, the common level of the output signal may be 1.2 V, or larger than this, or smaller than this voltage, for example.
However, particularly when the common level becomes low for the input signal of the same amplitude, the voltage at the gate terminal versus the voltage at the source terminal of each of the MOS transistors TN1 and TN2 does not easily exceed the own threshold voltage. Therefore, the waveform of the output signal collapses, and the duty of the output signal versus the duty of the input signal changes, for example. Further, when the common level has lowered to an extent that the voltage at the gate terminal versus the voltage at the source terminal of each of the MOS transistors TN1 and TN2 does not completely exceed the own threshold voltage, the differential amplifier does not operate at all.
It is an object of the present invention to provide a semiconductor integrated circuit capable of outputting a signal of which level changes in response to an input signal even when the common level of the input signal has varied.
The semiconductor integrated circuit according to one aspect of the present invention comprises a differential amplifier including a first MOS transistor having a gate terminal connected to a first node, a second MOS transistor having a gate terminal connected to a second node, and a third MOS transistor having a drain terminal connected to source terminals of the first and second MOS transistors respectively. Furthermore, a level detector circuit is detects an intermediate voltage level between two voltages of the first and second nodes respectively, and a bias generation circuit generates a bias voltage to be applied to a gate electrode of the third MOS transistor based on a voltage level detected by the level detector circuit.
The semiconductor integrated circuit according to another aspect of the present invention comprises a differential amplifier including a first MOS transistor having a gate terminal connected to a first node, a second MOS transistor having a gate terminal connected to a second node, and a third MOS transistor having a drain terminal connected to source terminals of the first and second MOS transistors respectively. Furthermore, a first element is connected between the first node and a third node, a second element is connected between the second node and the third node. Furthermore, a bias generation circuit generates a bias voltage to be applied to a gate electrode of the third MOS transistor based on a voltage level of the third node.